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AT26DF081A
10.1.6
10.1.7
WEL Bit
RDY/BSY Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is
in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect
Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a
device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati-
cally under the following conditions:
? Write Disable operation completes successfully
? Write Status Register operation completes successfully or aborts
? Protect Sector operation completes successfully or aborts
? Unprotect Sector operation completes successfully or aborts
? Byte/Page Program operation completes successfully or aborts
? Sequential Program Mode reaches highest unprotected memory location
? Sequential Program Mode reaches the end of the memory array
? Sequential Program Mode aborts
? Block Erase operation completes successfully or aborts
? Chip Erase operation completes successfully or aborts
? Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-
mand must have been clocked into the device.
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 10-1. Read Status Register
C S
0
1
2
3
4
5
6
7
8
9
10 11 12 1 3 14 15 16 17 1 8 1 9 20 21 22 2 3 24
S CK
OPCODE
S I
0
0
0
0
0
1
0
1
M S B
S TATU S REGI S TER DATA
S TATU S REGI S TER DATA
S O
HIGH-IMPEDANCE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
M S B
M S B
M S B
25
3600G–DFLASH–06/09
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